Silicon Carbide (SiC) has been recognized as the next generation semiconductor material to replace Si for high power and high frequency applications, particularly, under extreme conditions, such as high temperature and high radiation (e.g. in the space and nuclear reactors). In order to be used in industrial or military applications, the stability and reliability of the SiC diodes must be improved. However, the current technology of SiC PiN and PN diodes consistently exhibit a degraded forward voltage drop under constant forward current density during use. Failure rates in the fabrication of SiC diodes have been reported as high as 80%. This disadvantage of the present state of the art of SiC diodes has prevented their commercialization.
The disadvantages of SiC semiconductors is primarily related to material defects, particularly in the epitaxial layer of SiC diodes. Such defects behave as a deep energy level that traps carriers in the drift region of the diode, thereby reducing the carrier lifetime and increasing the forward voltage drop. Therefore, significant efforts to improve SiC material quality to reduce the defect density to a sufficient level to fabricate diodes without degradation is much needed.
The main obstacle in the fabrication of high power SiC PN and PiN junction diodes is the existence of defects that cause forward voltage drop degradation with time (voltage drift). This disadvantage is observed in diodes formed by both ion implantation and epitaxial growth. It is desirable to have the forward voltage drop to be as low as possible to reduce the on-state resistance of a diode. In addition, any voltage drop must be stable throughout the operating time of the diode. The initiation of diode degradation is associated with the generation and movement of structural defects such as stacking faults (SFs), in the active region of the diode. Stacking faults prevent the realization of long-term reliable SiC diodes. Thus far, no system or method for eliminating forward voltage drift in SiC diodes that have low forward voltage drops has been provided.
Degradation of forward voltage drop in SiC diodes destroys the usability of diodes. Referring now to Graph 1, the top curve represents incorrect performance of a SiC diode when forward voltage is applied to the diode. As the top curve shows, the forward voltage of the diode drops over time and degrades from approximately three volts to approximately 13 volts after approximately 1,500 seconds. Such quick failure has prevented the wide-spread commercialization of SiC diodes. However, SiC diodes that are produced by the invention described herein results in little to no degradation as shown in the lower curve of Graph 1. The voltage applied to produce a predetermined current of a SiC diode of this invention remains constant with little to no degradation. 
A principal reason for the generation of SFs in SiC diodes is the existence of stress in the crystalline lattice. Introduction of impurity atoms into a crystalline lattice causes mismatch stresses; atoms with smaller radii induce compressive strain while atoms with larger radii induce tensile strain. For proper operation of a device, the maximum concentration of dopant atoms at the contact ends (p+ or n+) must be high enough such as with a density greater than 1018 cm−3. However, an increase in the doping concentration can result in increase of mismatch stresses. If the mismatch stresses exceed the value of critical shear stress, crystal lattice defects such as dislocations are formed. The formed dislocations act as nucleation sites for the generation of stacking faults, and can be responsible for the degradation of SiC diode and result in disadvantageous forward current-voltage characteristics. In order to eliminate the degradation, it is necessary to reduce mismatch stresses that result in the formation of dislocations.
Conventional methods, such as ion implantation and epitaxial growth used to form PN junctions in SiC devices, generally, result in the formation of abrupt PIN junctions. High impurity concentration gradients in these types of junctions induce lattice stresses due to different radii of dopant and host atoms. If the value of the stresses exceeds the yield stress (˜1 MPa for SiC), mismatch dislocations might be generated. During the diode operation, the residual stresses may generate additional electrically active broken chemical bonds. These broken bonds can be carrier traps, which might result in an increase of the series resistance during PiN diode operation and, hence, in forward voltage drop increase.
Therefore, it is an object of this invention to provide a diode that does not have forward voltage drop degradation.
It is another object of this invention to provide a SiC diode that does not have forward voltage drop degradation.